Non-volatile memory devices organized and functioning in a page mode include a circuit, called a page buffer. The page buffer stores data to be programmed in the addressed locations of the memory cell array, and is to be read from addressed locations of the memory cell array. The page buffer includes a data driver for each memory cell of the page for outputting a read datum.
To understand the functioning of a page buffer during a read operation, reference is directed to the scheme of FIG. 1. Substantially, during every read operation, the data driver of the page buffer PAGE BUFFER transfers a datum DATA read from the respective memory cell to an output node of the buffer when an enabling signal PBDO is asserted.
The outputs of the data drivers are connected to the inputs of a multiplexer COLUMN MUX that selects the datum provided by a data driver identified by the address signals YA<i>, YB<i> and YC<i>. This selected datum is transferred to a global data line of the memory device by a global data line driver when a second enabling signal DOEN is asserted.
As depicted in FIG. 1, a datum read from a memory cell propagates through four transistors in cascade for reaching the global data line driver. If this datum is at the supply voltage level, the voltage drops on these transistors may be relevant and the signal nDL could not be at a voltage level sufficient to turn on the transistor N0.
Therefore, in this situation the signal nDL_N would remain high and thus, when the second enabling signal DOEN is asserted, the two-input inverter transfers an incorrect datum GDL to the global data line of the memory device. This drawback is likely to occur when the memory is functioning with a relatively low supply voltage (1.8V, for example).
This problem may be overcome in architectures of memory devices that include a global data line driver, as depicted in FIG. 2. In these memory devices, the global data line driver usually includes a pre-charge transistor P0 for connecting/disconnecting the input line of the global data line driver to a supply voltage line of the memory device. The pre-charge transistor P0 is switched on by the control signal PRE_N when the enabling signal PBDO of the data driver of the page buffer is asserted, and when a low (supply) voltage functioning mode of the memory device is selected. This low voltage functioning mode is usually selected by switching high an externally provided logic command SUPPLY18.
With the above approach, the datum is correctly transferred to the global data line even when functioning in low voltage mode. Unfortunately, in memory devices that include the circuit of FIG. 2, power consumption is found to be greater than in memory devices with the circuit of FIG. 1.
The memory devices that include the circuit of FIG. 2 are more power consuming than the memory devices that include the circuit of FIG. 1 because of a small, though significant, flow of current through the transistor P0 even in a stand-by state.
This current is very small even when the datum nDL is low because the transistor P0 usually has a relatively large resistance, even in a conduction state. This increase of current absorption of the pre-charge transistor P0 exists even when the datum nDL is low. In a memory device, there are many global data line drivers, and the currents absorbed by them when the memory is in a stand-by state and when the read datum nDL is low add up.